Compressed Bit Fail Maps for Memory Fail Pattern Classification
نویسندگان
چکیده
This paper presents a new approach to configure compressed bit fail maps to allow fail pattern recognition. Construction of the special compression scheme will be shown. This takes typical memory array fail patterns into account. Examples for different failure types are given. This scheme allows minimizing the necessary catch memory size for fail classification. A 64Mbit fail map can be compressed to 2k allowing classification of 13 fail types. Since catch ram requirements are small, this scheme can be implemented in a manufacturing environment for all processed hardware. Compressed bit fail maps can be used to generate wafer and lot maps for diagnosis.
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عنوان ژورنال:
- J. Electronic Testing
دوره 17 شماره
صفحات -
تاریخ انتشار 2001